Implementation and optimization of asymmetric transistors in advanced SOI CMOS technologies for high performance microprocessors
FREE-DOWNLOAD- J Hoentschel, A Wei, M Wiatr… – … , 2008. IEDM 2008. It has become extremely challenging for EOT scaling to keep pace with gate length reduction in advanced technology generations. This has resulted in non-optimal transistor electrostatic integrity, performance, and reliability tradeoffs. At a given EOT, however, a transistor with an asymmetric channel configuration can offer several advantages in […]
45nm High-k+ metal gate strain-enhanced transistors
FREE-DOWNLOADC Auth, A Cappellani, JS Chun… – VLSI Technology, …, 2008 Two key process features that are used to make 45nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-k transistors. The second feature is the extension of 193nm dry lithography […]
Fast Thermal Analysis of Vertically Integrated Circuits (3-D ICs) Using Power Blurring Method
FREE-DOWNLOAD JH Park, A Shakouri… – Proc. of the InterPACK …, 2009 . ABSTRACT CMOS VLSI technology has been facing various technical challenges as the feature sizes scales down. . INTRODUCTION The evolution of CMOS VLSI technology has been driven by two main motives: to increase functionality and functional density.