Reordering of Test Vector Using Artificial Intelligence Approach for Power Reduction during VLSI Testing
Optimization of testing power is a major significant task to be carried out in digital circuit design. Low power VLSI circuits dissipate more power during testing when compared with that of normal operation. As the feature size is scaled down with process technology advancement, power minimization has become a serious problem for the designers as […]
VLSI Technology, Wafers and Impact on Nanotechnology
This paper presents a detailed study of the present VLSI technological aspects, importance and their replacement or combination with the Nanotechnology in the VLSI world of silicon semiconductors. Here authorsbringout the nanotechnologyinSiliconworldwhich invariably means shrinking geometry of CMOS devices to nano scale. This also refers to a new world of nanotechnology where chemists are working […]