ENGINEERING RESEARCH PAPERS

SRAM Design


A Robust SRAM Design for Ultra Dynamic Voltage Scalable VLSI System

FREE DOWNLOAD ABSTRACT. In this paper, a SRAM array targeting IBM 130nm CMOS technology is proposed for ultra dynamic voltage scaling (UDVS) application with better immunity against process variation. A type of modified Schmitt Trigger inverter is adopted in the SRAM design, which

Technologies for ultradynamic voltage scaling
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Standard CMOS logic gates are designed to yield noise- margins that are nearly half of VDD. Standard 6T SRAM bit- cells, however, have a read static-noise-margin (SNM) [40] and write-margin that is set by ratiometric interactions between devices, and these are thus

Circuit design advances for wireless sensing applications
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Additionally, the microprocessor can perform signal processing on the pressure data to check for abnormally 9(d)] improves read margin by cutting the feedback loop during accesses [44]. In addition to increased density, eDRAM can achieve higher read and write margins than

Ultra-Low Voltage Split-Data-Aware Embedded SRAM for Mobile Video Applications
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at 0.36 V under process variation and NBTI aging effect: 1) a hybrid 10T + 8T hybrid array to improve read static noise margin and reduce the read power simultaneously; 2) a SDA scheme to further increase the write margin and the write power efficiency; 3

DECOUPLING LOGIC BASED SRAM DESIGN FOR POWER REDUCTION IN FUTURE MEMORIES
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rate (SER), temperature, and process variations and parasitic transistor resistance, the scaling of SRAMs becomes increasingly difficult due to reduced margins . Fig However it did not improve noise margin and required a negative voltage during a read operation that

A Low Power Column-Decoupled 8TProcess
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(SER), temperature, and process variations and parasitic transistor resistance, the scaling of SRAMs becomes increasingly difficult due to reduced margins . Fig. 1 illustrates the 552-557. 7. Takeda, K., et al., A read-static-noise-margin-free SRAM cell for low-VDD and high-

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