vlsi research papers 2012-102
ENGINEERING RESEARCH PAPERS

vlsi research papers 2012-102




Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design
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S Wairya, RK Nagaria, S Tiwari ,International Journal ABSTRACT This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style

Design And Analysis Of VLSI Based FELICS Algorithm For Lossless Image Compression
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C TT II, C EE ABSTRACT In this research paper, the VLSI oriented FELICS (Fast Efficient Lossless Image Compression System) Algorithm is proposed to provide the lossless image compression applications such as Medical imaging, Technical drawings ect To analysis the

Low Power VLSI Techniques Using Booth Algorithm for Digital Filter for Hearing aid Applications
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AJP Namdeo ABSTRACT In the past few years there has been an explosive growth in the demand for portable computing and communication devices, from mobile telephones to sophisticated multimedia systems. This interest in these devices has enhanced the requirement of

VLSI Design of Secured Cryptosystem
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G Geetha, A Muthukrishnan ABSTRACT This project proposes Image cryptosystem scheme to achieve High speed and to improve the security level by using Discrete Wavelet Transform (DWT) and Chaos based approach in to the image. Internet now a day is one of the most popular modes of

LDPC Decoding: VLSI Architectures and Implementations
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K Gunnam ,flashmemorysummit.com Q, is cyclically shifted up by the amount (,) sln k is the check-node degree of the block row. A negative sign on (,) sln indicates that it is a cyclic down shift (equivalent cyclic left shift).)(· f denotes the check-node processing, which embodiments implement using, for example, a

VLSI Design of Low Power Booth Multiplier
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N Bano ABSTRACT This paper proposes the design and implementation of Booth multiplier using VHDL. This compares the power consumption and delay of radix 2 and modified radix 4 Booth multipliers. Experimental results demonstrate that the modified radix 4 Booth

Design of a Neural Network Based Image Recognition System Using Configurable VLSI
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ABSTRACT This paper describes the initial steps in the development of an object detection system for manipulation purposes to be embedded in a mobile robot. The goal is to design a neural network based recognition module. The neural network module and additional

Efficient VLSI Architecture for Memetic Vector Quantizer Design
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CM Ou, WJ Hwang ,cdn.intechopen.com

CIRCUIT MINIMIZATION IN VLSI USING PSOGA ALGORITHMS
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ABSTRACT Circuit partitioning is the more critical step in the physical design of various circuit in VLSI. In this partitioning main objective is to minimize the number of cuts. For this PSO algorithm is proposed for the optimization of VLSI inter connection (net list) bipartition.

A VLSI Implementation of FSM-based programmable Memory Built-In Self Test (MBIST) Controller
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S Hussain, Z Hussain, K Fatima ,irnetexplore.ac.in ABSTRACT This paper proposed a High speed FSM-based controller for programmable memory built-in self test for testing memory devices. The architecture of controller is designed to implement a new test algorithm named March CS which has less number of

N0VEL TECHNIQUE FOR SIGNAL CLASSIFICATION BASED ON NEURAL NETWORK IN VLSI
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ABSTRACT Wireless sensor network is highly data centric. Data communication in wireless sensor network must be efficient one and must consume minimum power. Every sensor node consists of multiple sensors embedded in the same node. Thus every sensor node is

Efficient Implementation of Low Density Parity Check (LDPC) Decoder In VLSI
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ABSTRACT The best error-correcting performance can be achieved by using non-binary low- density parity check (NBLDPC) codes. This can be of reduced decoding complexity with high cost efficiency and is mostly preferable than binary low density parity check codes.

Design Verification and Test of Digital VLSI Circuits-Video course
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S Biswas, JK Deka ,nptel.iitm.ac.in Digital VLSI Design flow comprises three basic phases: Design, Verification and Test. The video course would cover theoretical, implementation and CAD tools pertaining to these three phases. Although there can be individual full courses for each of these phases, the

VLSI IMPLEMENTATION OF AREA AND POWER EFFICIENT LUT AND MEMORY DESIGN FOR FIR DIGITAL FILTER
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P SANGEETHA, SK MOHIDEEN ABSTRACT FIR digital filter is widely used in various signal processing and image processing applications. The filter order determines the width of the transition band, as the order increases the number of MAC units required for filter output also increases linearly and

A Bus Encoding Method for Crosstalk and Power Reduction in RC Coupled VLSIInterconnects
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SK Verma, BK Kaushik ABSTRACT The performance factors such as propagation delay, power dissipation and crosstalk in RC modelled interconnects are major design issues for the System on-chip (SoC) designs in current Deep Submicron (DSM) era. The crosstalk effect is a

ANALYSIS OF R2 2 SDF PIPELINE FFT ARCHITECTURE IN VLSI
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M Kaur, P Kapoor ABSTRACT This paper explains the implementation of a R22 SDF Pipeline FFT Architecture using hardware description language VHDL simulated up to 20 MHz for transformation length 256-point. A hardware oriented radix-22 algorithm is derived by integrating a

DESIGN FOR TESTABILITY ARCHITECTURE USING THE EXISTING ELEMENTS OF CP-PLL FOR DIGITAL TESTING APPLICATIONS IN VLSI ASIC DESIGN
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A Tiwari, AK Sahu, GR Sinha ABSTRACT This paper proposes a novel approach for testing applications useful in mixed signal ICs (here CP-PLL) by involving the existing components for DFT. The proposed method uses the charge pump as stimulus generator and the VCO as measuring device

SYSTEMATIC DESIGN OF HIGH-SPEED AND LOW-POWER DIGIT-SERIAL MULTIPLIERS VLSIBASED
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ABSTRACT Terms of both latency and power Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial architectures obtain using traditional unfolding techniques cannot be

An ELITIST AREA-POWER DENSITY TRADE-OFF in VLSI FLOORPLAN USING GENETIC ALGORITHM
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ABSTRACT Due to trade-offs between the VLSI circuit parameters, chip suffers from reliability issues. It needs to be optimizing for better performance. Such problems are defined as NP- hard problems. In this paper a heuristic has been developed using genetic algorithm for

An Enhanced Carry Elimination Adder for Low Power VLSI Applications
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V Muralidharan, M Jagadeeswari ABSTRACT Truncation and round off errors in adders has become unavoidable in modern VLSI technology. A new type of adder ie error tolerant adder (ETA) is proposed to tolerate those errors and to attain low power consumption and high speed performance in DSP

COMPARISON AMONG DIFFERENT CMOS INVERTER WITH STACK KEEPER APPROACH INVLSI DESIGN
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H UPADHYAY, A CHOUBEY, K NIGAM ABSTRACT For the most recent CMOS feature sizes (eg, 90 nm and 65 nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. Leakage power consumption of current CMOS technology is already a great challenge. International

Design of a Multiplexer In Multiple Logic Styles for Low Power VLSI
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M Padmaja, VNVS Prakash ABSTRACT The Low power and low energy has become an important issue in today s consumer electronics. Any combinational circuit can be represented as a multiple inputs with single output. Multiplexers are used to design any digital combinational logic circuit.

VLSI Architecture for 1-D Lifting Discrete Wavelet Transform
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SS Nayak, N Nayak ,estdl.org ABSTRACT VLSI architecture for 1-D lifting DWT is proposed in this paper. All resolution levels are folded to same high-pass and low-pass filters. Hardware utilisation of the proposed architecture is very high. Compared with other known architectures, the proposed

A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
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G Knagge ,project.sigpromu.org ABSTRACT Multiuser detection (MUD) strategies have the poten-tial to significantly increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits that cope with real world situations and

VLSI Implementation of Residue Adder and Subtractor
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O Dajani, G Bawa, H Singh ,elrond.informatik.tu-freiberg.de ABSTRACT In the present world there is always a demand for faster algorithms and techniques that could boost up the speed of the computations. With the help of VLSI fabrication techniques and using residue number system (RNS) arithmetic we can achieve the faster

A VLSI Approach for Cache Compression in Microprocessor
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MN Sharada Guptha, HS Pradeep, MZ Kurian ABSTRACT Speed is one of the important issues that generally customers consider for selecting any electronic component in the market. Speed of a microprocessor based system mainly depends on the speed of the microprocessor which in turn depends on the memory

Impedance Matching in VLSI Systems
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DMJ Alejandro, LD Edgar, AHJ Erasmo ,cdn.intechopen.com The continuous scaling process into submicrometric dimensions of silicon based devices has allowed the integration of a large number of systems in a single chip. Besides, the operating frequencies of such systems are higher and a large amount of information can

A VLSI ALGORITHM FOR THE HARDWARE IMPLEMENTATION OF 1-D DISCRETE SINE TRANSFORM BASED ON A PSEUDO-BAND CORRELATION
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ABSTRACT. Using a novel input restructuring sequence and appropriate index-mapping techniques a new VLSI algorithm for a prime-length DST is presented. The proposed algorithm uses a modular and regular computational structure, called pseudo-band

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