Design of Low Noise Low Power Linear CMOS Image Sensors
The implementation of active pixel based image sensors in CMOS technology is becoming increasingly important for producing imaging systems that can b e manufactured with low cost, low p ower, simple interface, and with good image quality. The major obstacle in the design of CMOS imagers is Fixed Pattern Noise (FPN) and Signal-to-Noise-Ratio (SNR) of […]
Low power Pipeline ADC
Low power Pipeline ADC
Low power Pipeline ADC
A 3.3V, 10bit, 80MS/s pipeline analog to digital converter is implemented in a 0.35um CMOS technology. Emphasis was placed on low power circuit design and system simulation was done to guide the circuit design. A Two-stage comparator and a high performance Op-amp were designed. The achieved ENOB is 9.61 bits. Maximum INL and DNL are […]