Virtuoso Multi-Mode Simulation MMSIM
Comprehensive design and verification with the industry’s leading simulators Virtuoso Multi-Mode Simulation offers a complete verification solution for silicon realization • Virtuoso AMS Designer Verification Option for advanced SoC verification These simulators support a common syntax, use common device model equations, and are fully integrated into the Virtuoso Analog Design Environment and the Cadence Incisive® […]
VLSI design automation
Electronic design automation, also referred to as electronic computer-aided design, is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Algorithms for VLSI design automation free downloadAlgorithms for […]
FPGA FIELD PROGRAMMABLE GATE ARRAY IEEE PAPERS
FPGA and CPLD architectures: A tutorialfree download This article provides a tutorial survey of architectures of commercially available high- capacity field-programmable devices (FPDs), and gives a summary of recent research results in the field. In the survey section, we first define the relevant terminology in the field Programming models for hybrid FPGA -CPU computational components: […]
VHDL IEEE PAPERS
VHDL (VHSIC-HDL) (Very High Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. A study of the experimental validation of fault-tolerant systems using different VHDL -based fault injection techniquesfree download A Study of the […]
DCT DISCRETE COSINE TRANSFORM ARCHITECTURE-VLSI PROJECT
Low power and area efficient DCT architecture for low bit rate communicationfree download In this paper a low power and area efficient DCT (Discrete Cosine Transform) pipelined architecture using multiplier-less method is presented for low bit rate communications such as videoconferencing in mobile devices. The multiplier-less multiplication is implemented by Design of analog vlsi architecture […]
FFT FAST FOURIER TRANSFORM PROCESSOR-VLSI PROJECT
Efficient FPGA implementation of FFT /IFFT processor free download The Fast Fourier Transform ( FFT ) and its inverse (IFFT) are very important algorithms in signal processing, software-defined radio, and the most promising modulation technique; Orthogonal Frequency Division Multiplexing (OFDM). This paper explains the Reconfigurable VLSI architecture for FFT processor free download This paper presents […]
DIFFERENTIATOR VLSI PROJECT
Design of fractional order differentiator integrator circuit using RC cross ladder networkfree download In this paper the concept of FRACTIONAL ORDER‟ element is reported. RC ladder network itself behaves as a fractional order element which is developed and the same ladder network is been used in Integer order differentiator and integrator circuit to make it […]
HIGH SPEED COMPARATOR-VLSI PROJECT
Design of a CMOS comparator for low power and high speed free download This paper reports comparator design for low power high speed . The present Design is specially design for high resolution Sigma Delta Analog to Digital Converters (SDADCs). Design is based on two stage CMOS OP-AMP technique. Simulation results have been Comparator for […]
BINARY TO GRAY CODE CONVERTER-VLSI PROJECT
High Performance Binary to Gray Code Converter using Transmission GATEfree download This paper gives an idea to improve power efficiency and effective area of binary to gray code converter using very popular transmission gate technology. Some sensors send information in gray code . So this must be important to convert a given binary stream into […]
CLOCK GATING-VLSI PROJECT
Power reduction through RTL clock gating free download This paper describes a design methodology for reducing ASIC power consumption through use of the RTL clock gating feature in Synopsys Power Compiler. This feature causes inactive clocked elements to have clock gating logic automatically inserted which reduces A review of clock gating techniquesfree download The synchronous […]