ADC-Analog to digital converter research papers recent 2014




A 10-Bit 800-MHz 19-mW CMOS ADC.
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Abstract:A pipelined ADC employs charge-steering op amps to relax the trade-offs among speed, noise, and power consumption. Such op amps afford a fourfold increase in speed and a twofold reduction in noise for a given power consumption and voltage gain.

IMGN779:targetED ANTIBODY-DRUG CONJUGATE (ADC) UTILIZING A NOVEL DNA ALKYLATOR, DGN462, IS HIGHLY ACTIVE IN VITRO AGAINST
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Increased colony formation was also observed in long-term cultures of NBM after treatment with IMGN779, indicating that HSCs are spared. M e dia n Tum or V o lum e (m m 3 ) IMGN779:targetED ANTIBODY-DRUG CONJUGATE (ADC) UTILIZING A

Developmental brain ADC atlas creation from clinical images
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Results: The detailed data request submitted to RPDR returned the EMRs of 4745 pediatric patients with a head MRI. From them 1600 patients were< 6yr at the time of scan, with potentially normative brain MRI acquired after 2006. In this preliminary study we included

Structure of ADC-68, a novel carbapenem-hydrolyzing class C extended-spectrum b-lactamase
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Acinetobacter baumannii is increasingly being recognized as a crucial pathogen that is associated with nosocomial infections and is frequently involved in infectious outbreaks in intensive care units and burns units (Bergogne-Bérézin Towner, 1996; Poirel

Reference Circuit Design for a SAR ADC in SoC
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A typical Analog-to-Digital Converter (ADC) compares an input voltage with a reference voltage and generates a digital code corresponding to the input voltage level. Equation 1 on page 1 gives the relation between ADC outputs and input and reference voltage for an

A 4-Bit 8GS/s Flash ADC in 0.18 µm CMOS Technology
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Abstract A 4-bit 8GS/s flash Analog-to-Digital Converter is designed and simulated in a 0.18 µm CMOS technology. To enhance the speed, both of analog (comparators) and digital (encoder) parts of the ADC are designed fully pipelined using CML gates and latches.

Discrimination between Intact and Decayed Pulp Regions in Carious Teeth by ADC Mapping
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Abstract The aim of this study was to evaluate an advanced magnetic resonance imaging (MRI) method, apparent diffusion coefficient (ADC) mapping, in the functional assessment of carious teeth. 38 extracted human teeth with scores of 0, 3 and 6 according to

ADC test library in LabVIEW
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Abstract–ADC testing requires post processing of the acquired data for the estimation of ADC parameters. LabVIEW, as a very popular tool for development of various control and measurement applications, offers many specialized toolkits and libraries, but a specialized

DESIGN OF FIFTH ORDER CONTINUOUS TIME-DELTA SIGMA ADC USING SIMSIDES
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Abstract:This paper brief the use of very high precision Noise shaping sigma delta modulation techniques for high applications that require a signal-to-noise ratio and high resolution. A continuous-time delta-sigma A/D modulator with OSR of 40, signal

Adc test tool for labview
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Abstract–An easy-to-use LabVIEW tool for ADC testing is presented. The tool provides a comprehensive collection of data processing algorithms which are able to ensure the best possible results in ADC testing, and to help to recognize bad parameter settings during

A New Design Methodology for Voltage-to-Time Converters (VTCs) Circuits Suitable for Time-Based Analog-to-Digital Converters (T-ADC)
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Abstract:Voltage-to-Time Converter (VTC) circuit is considered one of the essential blocks in the design of Time-based Analog-to-Digital Converters (T-ADCs). T-ADC is a promising candidate for Software Defined Radio (SDR) receivers that require wide band and high

A Low-Voltage Low-Power Opamp-Less 8-bit 1-MS/s Pipelined ADC in 90-nm CMOS Technology
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Abstract: This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7 V and 0.5 V, respectively. This low power ADC utilizes the capacitive charge pump technique

A 1.1 V 81.8 dB Delta-Sigma ADC.
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Abstract A 1.1 V 81.8 dB delta-sigma analog-to-digital converter (ADC) is presented. The split time integration technique for implementing multi-bit digital-to-analog converter (DAC) without using DEM has been developed and used. In order to reduce power consumption

http://adc. bmj. com
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Conclusions Children with CHD risk lower performance on intelligence and neurocognitive skills. Only executive function reaction time showed a large effect size. A high diversity in research practices and small sample sizes were also ascertained. Large, more

MPC57xx SAR ADC Implementation and Use
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Analog-to-Digital Converters (ADCs) are used in a rapidly increasing number of automotive applications. From simply monitoring DC voltages to supporting radar detection of obstacles in ADAS solutions, ADCs find wide acceptance in automotive Micro Controller Units (

ADC Testing in Standardized and Non-standardized Ways, Executed in a Unified Framework
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Abstract–Several test methods are available to examine static and dynamic properties of analog-todigital converters (ADCs). The most robust and straightforward ones are codified in international standards released by the IEEE, or by the IEC. These methods have been

A Versatile 1.4-mW 6-bits CMOS ADC for Pulse-Based UWB Communication Systems
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Abstract: An ADC (analog to digital converter) using the low duty-cycle nature of pulse- based UWB (ultra wide-band) communications to reduce its power consumption is proposed. Implemented in CMOS (complementary metal-oxide-semiconductor) 180 nm

A Low-Power MOS-Only Potentiostatic S ADC Architecture for Electrochemical Sensors
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Nov 2014 Intro Arch Circuits Monolithic Results Conclusions A Low-Power MOS-Only Potentiostatic S ADC Architecture for Electrochemical Sensors Page 2. Intro Arch Circuits Monolithic Results Conclusions S ADC architecture for potentiostatic biasing and

Differential Non Linearity and Integral Non Linearity Estimation of 4-bit Flash ADC using (CDC)
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Abstract: The Comparator is the vital part of ADC The design of Comparator decides the performance of ADC. The purpose of ADC is to convert Continuous changing input signal into respective digital signal. The input signal varies with time and amplitude so we

Evaluation of Vertebral Bone Marrow with Diffusion Weighted MRI and ADC Measurements
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Evaluation of Vertebral Bone Marrow with Diffusion Vertebral Kemik Iliginin Difüzyon Agirlikli MRG ve ADC Ölçümleri ile Degerlendirilmesi Objective: The purpose was to determine the usefulness of DWI and ADC in the evaluation of vertebral bone marrow. Methods:

An Innovative Design of ADC and DAC Based Phase Locked Loop
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Abstract:The project aims at designing an analog phase locked loop based on digitally controlled feedback loop wherein the digital control loop gathers the locking information in digital blocks. The loop consists of analog components such as phase detector, loop and

Development of multichannel analyzer using sound card ADC for nuclear spectroscopy system
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Abstract. This paper describes the development of Multi-Channel Analyzer (MCA) using sound card analogue to digital converter (ADC) for nuclear spectroscopy system. The system was divided into a hardware module and a software module. Hardware module

Low-Noise Circuits for Precision ADC of Amplitude
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Abstract This report presents a new low-noise circuit to digitize the peak value of a waveform. When applied to sine waves, this circuit allows very accurate measurement of the amplitude. Thus, it presents a new unusual type of low-noise ADC which performs

Euclidean quadratic forms and ADC forms II: integral forms
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Page 1. EUCLIDEAN QUADRATIC FORMS AND ADC-FORMS II: INTEGRAL FORMS PETE L. CLARK AND WILLIAM C. JAGY Abstract. Contents 1. Introduction 2 1.1. Background and Prior Work 2 1.2. ADC Forms over Z 4 1.3. Euclidean Forms over Z 5 1.4. Acknowledgements

A fast, low-power, multichannel 6-bit ADC ASIC with data serialisation
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Future particle physics experiments will require more functionality in the readout systems of particle detectors. In particular, front-end electronics is expected to perform more signal processing than it is usually done in present readout systems. A natural solution to this

Design and Implementation of a Low Power Second Order Sigma-Delta ADC
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Abstract:Sigma-Delta (-) analog to digital converters are well known for its use in high accuracy wireless communication applications. It is alternative for low power, high resolution (greater than 12 bits) converters, which can be ultimately integrated on digital signal

A 10-BIT 25 MS/S PIPELINED ADC USING 1.5-BIT SWITCHED CAPACITANCE BASED MDAC IN 180NM CMOS
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ABSTRACT The primary motivation of the work presented in this paper is to significantlyreduce power consumption in pipelined ADCs using Switched Capacitance based MDAC with Opamp Sharing configuration. ADC power reduction enables

VLSI DESIGN OF 12-BIT ADC WITH 1GSPS IN 180NM CMOS INTEGRATING WITH SAR AND TWO-STEP FLASH ADC.
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ABSTRACT In this paper, a Novel Hybrid ADC consisting of two-step quantizer which has Flash ADC and SAR ADC along with Resistor String DAC is designed and implemented. This Hybrid ADC improves the speed by employing Flash ADC and resolution and power

Designing With MSP430FR58xx/FR59xx/68xx/69xx ADC
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ABSTRACT Designing an application with the analog-to-digital converter (ADC) requires several considerations to optimize for power and performance. This application report discusses the basics of how you would analyze a data sheet and user's guide to design

A Segmented DAC based Sigma-Delta ADC by Employing DWA
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Abstract Data weighted averaging algorithm work well for relatively low quantization levels, it begin to present significant problems when internal quantization levels are extended farther. Each additional bit of internal quantization causes an exponential increase in the

Applied-Information Technology in Sigma-Delta ADC Based on P87LPC764
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Behavioral non-ideal Model of 8-bit Current-Mode Successive Approximation Registers ADCby using Simulink.
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Abstract In this paper a new non-ideal model of 8-bit Current Mode Successive Approximation Analog-Digital Converter (CM-SAR-ADC) has been proposed, the main blocks of CM SAR ADC are a current sample and hold, a current comparator, SAR logic

LINEARITY ANALYSIS OF SPLIT SAR ADC USING Vcm BASED SWITCHING AND SWITCHBACK SWITCHING FOR WIRELESS SENSOR NETWORK
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ABSTRACT: As advanced CMOS technologies enhance the prepared speed of logic circuit significantly. Successive approximation register (SAR) analog-to-digital converter is wellmatched with the standard CMOS process with low provides voltage, because it does

ESTIMATION OF STATIC AND DYNAMIC PARAMETERS OF FLASH ADC USING 180 NM TECHNOLOGY
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Abstract:This paper presents the design of Analog to Digital Convertor (ADC). For ADC there are mainly four different methods, Flash ADC, Pipelined ADC, Successive Approximation ADC, Sigma Delta ADC. The Flash ADC is the Fast ADC. For Designing

12-Bit Pipeline ADC Implemented in 0.09-um Digital CMOS Technology for Powerline Alliance
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Abstract:This paper presented its own design of 12-bit pipeline ADC which has an operating frequency of 8 MHz and consists of 4 stages only. This design is a pipelined ADC with four 3-bit stages (each stage resolves two bits). By doing so, the chip area can be

Multi-input Synchronous Analog-to-Digital Converter
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Abstract:Integration of multiple synchronous identical superconductor analog-to-digital converters (ADCs) on a single chip or a multi-chip module is attractive for numerous applications, including Magnetic Resonance Imaging (MRI) systems. Several dual-ADC
Abstract: To design a low-power, high-speed and highresolution analog-to-digital converter (ADC) in sub-100 nm technology, this paper presents a technique using folding integration (FI) and digital calibration. We have compared the circuit simulation results

Photonic Time-Stretched Analog-to-Digital Converter with Suppression of Dispersion-induced Power Fading Based on Polarization Modulation
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Abstract:A photonic time-stretched analog-to-digital converter with suppression of dispersion-induced power fading is proposed using polarization modulation. A 32-GHz single-tone input, which should undergo the largest dispersion impairment, is

A Low-Power High-Speed Single Ended CMOS Comparator For Flash Analog to Digital Converter
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Abstract:This paper presents a new low power CMOS comparator for flash analog to digital converter (ADC). The proposed comparator has single-ended type of architecture. The comparator is designed and analyzed by Cadence Virtuoso Analog Design Environment

DESIGN OF 6-BIT FLASH ANALOG TO DIGITAL CONVERTER USING VARIABLE SWITCHING VOLTAGE CMOS COMPARATOR
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ABSTRACT This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the cost of high power consumption. By using the new

Design of a Low Power, High Speed Analog to Digital Pipelined Converter for High Speed Camera CMOS using 0.18 µm CMOS Technology
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Background: In this work one presented the design analog to digital Converter (ADC) of pipeline type of 3bits, 10MS/s and a low power consumption for high speed camera CMOS. The OTA plays an important role in the ADC, because of its conversion rate and power

DESIGN OF LOW POWER DISCRETE TIME SIGMA-DELTA MODULATOR FOR ANALOG TO DIGITAL CONVERTER.
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ABSTRACT Modulator is one of the most significant building-blocks in integrated discrete time component used in Sigma-Delta (S) analog to digital converter. In this paper a novel structure of a switched-capacitor discrete time first order modulator Sigma-Delta is

Co 60 Gamma-Ray Effects on the DAC-7512E 12-Bit Serial Digital to Analog Converter for Space Power Applications
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Abstract–The DAC-7512E is a 12-bit digital to analog converter that is low power and a single package with internal buffers. The DAC-7512E takes up minimal PCB area for applications of space power electronics design. The spacecraft mass is a crucial point

3 rd–Order Dual Truncation 18-Bit Audio MASH 2-1 Delta-Sigma Digital to Analog Converterin 90nm CMOS Technology Implementation
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Abstract:A sigma-delta third order dual truncation MASH 2-1 D/A converter with 18-bit input format is successfully implemented in 90nm CMOS technology. This design focuses on the digital implementation of 64x upsampling digital interpolator and third-order delta-sigma

2-1, 2-2 and 2-1-1 MASH Delta-Sigma Modulator for 18-Bit Audio Digital to Analog Converter
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Abstract:MASH modulators are cascaded low order modulators that are designed to increase the fidelity of the output signal at the receiving end of the transmission medium. One sigma-delta third order dual truncation 2-1 MASH and two sigma-delta fourth order

Designing an Ultra Low Power Digital-to-Analog Converter: A 8-bit 144nW 40MHz 90nm D/A
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ABSTRACT: In this paper an ultra-low power Digital-to-Analog Converter (DAC) for ultra-low power applications is presented. A number of techniques are used to reduce the power consumption and relatively boost the speed of the DAC. These techniques include low

Design of Moderate Speed and Moderate Resolution Successive Approximation Analog to Digital Converter
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Abstract: This Paper presents the Design of analog to digital converter (ADC) for low power applications, so here is the selection of right architecture is very crucial. We have chosen successive approximation Analog to Digital Converter because of their compact circuitry

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