synchronous-programmable-divider-design-for-pll
Synchronous programmable divider design for PLL Using 0.18 um cmos technology
Suchitav Khadanga
RFIC design consultant, Bangalore, India
Abstract
In the wireless communication market, trends are moving towards smaller size, fewer parts, longer lifetime and higher frequency operation. These trends imply that wireless communications circuits must incorporate higher integration and that their design and IC technology must be optimized for low power and high frequency system. One innovative method to increase the frequency of programmable divider is discussed. The new method not only increases the frequency of operation but also decreases circuit complexity and power dissipation. This new design use synchronous counters instead of asynchronous counters. The digital gates are optimized for minimum propagation delay and loading effect using progressive sizing of the transistors. This is better configuration in every aspect in terms of frequency, power dissipation and chip area.
Index terms: CMOS integrated circuits, frequency synthesizers, phase locked loop, programmable divider, Prescaler, PLL.
1. Introduction
The scaling of CMOS technologies to deep submicron has made CMOS a technological option for the low-gigahertz frequency range. However, for CMOS to become a commercial option for RF building blocks requires compliance to all trends of the consumer market: miniaturization, low cost, high reliability and long battery lifetime. Bulk CMOS technologies presently available satisfy the low cost and reliability trends by standard design practice. Complying with miniaturization and long battery lifetime, on the other hand, demands CMOS building blocks with low-power dissipation and good electromagnetic compatibility (EMC) characteristics. A critical RF function in this context is the frequency synthesizer, more particularly the programmable frequency divider. The divider consists of logic gates Which operate at RF frequency, Due to the divider’s complexity, high operation frequency normally leads to high power dissipation. Other crucial aspects of the present-day consumer electronics industry are the short time available for the introduction of new products in the market, and the short product lifetime. On top of that, the lifespan of a given CMOS technology is also short, due to the aggressive scaling of minimum feature sizes. Short time-to-market demands architectures providing easy optimization of power dissipation, fast design time and simple layout work. High reusability, in turn, requires an architecture, which provides easy adaptation of the input frequency range and of the maximum and minimum division ratios of existing designs. The choice of the divider architecture is therefore essential for achieving low-power dissipation, high design flexibility and high reusability of existing building blocks. A modular architecture complies with these requirements, as shall be demonstrated in this paper.
The divider can be implemented using static or dynamic cmos circuits. Dynamic circuit techniques evolved in the last few years into several cmos circuit technique such as domino, NORA, TSPC circuits. Nevertheless, the field of CMOS integrated circuits has reached a level of maturity, where it is now mainstream technology for higher integration density, low power consumption. Therefore, we had chosen cmos to design the programmable divider. The designed dividers have increased frequency capability with reduction of propagation delay using synchronous counters instead of asynchronous counters. The focus of the paper is first on the truly modular architecture and on the implementation of the circuits. Then the description of circuits with their behavior inside the programmable divider is described. Finally, a collection of measured data and the conclusions are presented.
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